1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to an overdriving operation and an internal voltage generation operation of a semiconductor memory device.
2. Description of the Related Art
The continuous scale-down of a line width and a cell size of a semiconductor memory chip is accelerating the reduction in power consumption of a semiconductor memory chip. As a result, the design technology for satisfying performance required in a low-voltage environment has been developed.
The most of semiconductor memory chips supply voltages to internal circuits for their operation by using an internal voltage generation circuit. The internal voltage generation circuit typically receives an external power supply voltage VDD from an exterior to generate an internal voltage.
A memory element such as a dynamic random access memory (DRAM), which utilizes a bit line sense amplifier, uses a core voltage VCORE to sense cell data.
When a word line selected and activated by a row address, data of a plurality of memory cells connected to the selected word line is delivered to bit lines, and a bit line sense amplifier senses and amplifies a voltage difference between a pair of bit lines.
In general, since several thousands of bit line sense amplifiers operate at the same time, a large amount of current may be consumed at a time at a terminal of a core voltage (VCORE) used to drive a pull-up power line RTO of the bit line sense amplifier.
However, in the trend of a lower operation voltage, there is a limitation in amplifying data of many cells using a core voltage VCORE at a time.
Accordingly, a bit line sense amplifier overdriving method has been adopted. In the initial operation of the bit line sense amplifier, that is, immediately after charge sharing between a memory cell and a bit line, the pull-up power line RTO of the bit line sense amplifier is driven by an overdriving voltage (typically, an external power supply voltage VDD) having a level higher than the core voltage VCORE for a certain time.
As described above, when the external power supply voltage VDD input from an exterior is used as the overdriving voltage, data of many cells may be stably amplified at a time by using a current of which amount is adequately ensured.
However, since the level of the power supply voltage VDD is relatively very higher than the target level of the core voltage, it takes a long time to return to the target level of the core voltage. That is, the voltage level of the pull-up power line RTO may not immediately return to the target level of the core voltage even after an overdriving operation period.
To rapidly drop the voltage level of pull-up the power line RTO, which has been increased by the overdriving operation, to the target level of the core voltage VCORE after the overdriving operation period, a discharge driving method has been adopted to instantaneously discharge the pull-up power line RTO to reach the target level of the core voltage VCORE.
FIG. 1 is a detailed circuit diagram illustrating the configuration of a bit line sense amplifier array of a semiconductor memory device adopting an overdriving method and a discharge driving method in accordance with the conventional art.
Referring to FIG. 1, the bit line sense amplifier array includes a bit line sense amplifier 30, an upper bit line separation unit 10, a lower bit line separation unit 50, a bit line equalize/precharge unit 20, a column selection unit 40, and a bit line sense amplifier power line driving unit 60.
The upper bit line separation unit 10 selectively separates/connects an upper memory cell array from/to the sense amplifier 30 in response to an upper separation signal BISH, and the lower bit line separation unit 50 selectively separates/connects a lower memory cell array from/to the sense amplifier 30 in response to a lower separation signal BISL.
When an enable signal is activated to drive a pull-down power line SB and a pull-up power line RTO at a set voltage level, the bit line sense amplifier 30 senses a voltage difference between a pair of bit lines BL and BLB, which are in a charge-sharing state and have a minute voltage difference therebetween, and amplifies voltages of the bit lines BL and BLB respectively to a ground voltage VSS and a core voltage VCORE or otherwise.
The bit line equalize/precharge unit 20 precharges the pair of bit lines BL and BLB to a level of a bit line precharge voltage VBLP (typically, VCORE/2) in response to a bit line equalize signal BLEQ after sense amplification and restoration processes for the bit lines are ended.
When a read command is applied, the column selection unit 40 delivers data sensed/amplified by the sense amplifier 30 to segment data buses SIO and SIOB in response to a column selection signal YI.
The bit line sense amplifier power line driving unit 60 includes an NMOS transistor M2 acting as a driver for normal driving, an NMOS transistor M3, an NMOS transistor M1 acting as a driver for overdriving, an NMOS transistor M4 acting as a driver for discharge driving, and a bit line sense amplifier power line equalize/precharge section 62.
The NMOS transistor M2 drives the power line RTO by using a voltage applied to the core voltage (VCORE) terminal in response to a pull-up power line driving control signal SAP activated in a normal driving period. The NMOS transistor M3 drives the power line SB by using the ground voltage VSS in response to a pull-down power line driving control signal SAN. The NMOS transistor M1 drives the power line RTO by using the external power supply voltage VDD in response to an overdriving pulse SAOVDP activated in an overdriving period. The NMOS transistor M4 drives the power line RTO by using the ground voltage VSS in response to a discharge driving pulse SADCDP activated in a discharge driving period. The bit line sense amplifier power line equalize/precharge section 62 precharges the power line RTO and the power line SB of the bit line sense amplifier 30 by using a bit line precharge voltage VBLP in response to the bit line equalize signal BLEQ.
Here, the case has been described, in which the overdriving pulse SAOVDP and the discharge driving pulse SADCDP are defined as a high active pulse, the NMOS transistor M1 is used as the driver for overdriving, and the NMOS transistor M4 is used as the driver for discharge driving. However, a PMOS transistor may be used as the driver for overdriving and the driver for discharge driving. As a transistor controlled by the pull-up power line driving control signal SAP, a PMOS transistor may be used instead of the NMOS transistor M2,
FIG. 2 is a timing diagram illustrating a change in the voltage level of the power line RTO of the bit line sense amplifier at the sense amplification operation of the semiconductor memory device adopting the overdriving method and the discharge driving method in accordance with the conventional art shown in FIG. 1.
Referring to FIG. 2, since the power line RTO of the bit line sense amplifier is driven by the external power supply voltage VDD when the overdriving pulse SAOVDP is activated and an overdriving period OVERDRIVE starts, the voltage level of the power line RTO of the bit line sense amplifier rapidly rises and reaches the level of the external power supply voltage VDD.
Then, when the overdriving pulse SAOVDP is deactivated and the overdriving period OVERDRIVE ends, the power line RTO is not driven by the external power supply voltage VDD, and the voltage level of the power line RTO rapidly falls. At this time, the voltage level of the power line RTO rapidly falls, but does not reach the level of the core voltage VCORE. This is because an operation (a bit line sense amplification operation) rapidly using charge loaded on the power line RTO has been already performed in the overdriving period OVERDRIVE and thus the voltage level of the power line RTO falls through the natural discharge of charge after the overdriving period OVERDRIVE.
Accordingly, the conventional art controls the discharge driving operation to be performed after the overdriving operation is performed. That is, when the discharge driving pulse SADCDP is activated and a discharge driving period RELEASE starts, the voltage level of the power line RTO, which has fallen to a voltage level higher than the level of the core voltage VCORE by a certain degree after the overdriving period OVERDRIVE ends, rapidly falls to the level of the core voltage VCORE.
In the semiconductor memory device adopting the overdriving method and the discharge driving method in accordance with the conventional art as described above, in order to drop the voltage level of the power line RTO in the discharge driving period RELEASE, a method of connecting the power line RTO to a ground voltage (VSS) terminal during the discharge driving period RELEASE is used, thereby allowing the voltage level of the power line RTO to reach the level of the core voltage VCORE.
However, in connecting the power line RTO to the ground voltage (VSS) terminal means that the charge loaded on the power line RTO is discarded.
That is, since the voltage of the power line RTO to be lowered in the discharge driving period is a part of power provided through the overdriving operation, discarding the power by connecting the power line RTO to the ground voltage (VSS) terminal in the conventional art represents that a part of power provided to the semiconductor memory device is wasted.
The amount of the power wasted in the conventional art as described above may be considered to be relatively small. However, since an operation for sensing/amplifying bit lines is very frequently performed and is always performed in the semiconductor memory device during the operation of the semiconductor memory device, the collected amount of the wasted power may be considerable.